Field
The described embodiments relate to memories in electronic devices. More specifically, the described embodiments relate to dynamically configuring regions of a main memory in a write-back mode or a write-through mode.
Related Art
Many modern computing devices (e.g., laptop/desktop computers, smart phones, set-top boxes, appliances, etc.) include a processing subsystem with one or more caches. Caches are generally smaller, fast-access memory circuits located in or near the processing subsystem that can be used to store cache blocks that are retrieved from lower levels of a memory hierarchy in the computing device (i.e., other, larger caches and/or memories) to enable faster access to the stored cache blocks.
In some of these computing devices, caches are operated in a write-through mode. In the write-through mode, when a cache block with modified data is written in a cache (i.e., stored to the cache), the cache block is also immediately forwarded to a next lower level of the memory hierarchy to be written in the next lower level of the memory hierarchy. By forwarding the cache block in this way in the write-through mode, the cache is kept consistent with the next lower level of the memory hierarchy. However, operating in the write-through mode incurs costs in terms of bandwidth consumption, processing time, delay, etc. related to forwarding each cache block from the cache to the next lower level of the memory hierarchy.
In some of these computing devices, caches are operated in a write-back mode. In the write-back mode, cache blocks with modified data can be written to a cache without being immediately forwarded to the next lower level in the memory hierarchy. Thus, the cache can include cache blocks with data that is different than the data in the same cache block in the next lower level of the memory hierarchy. In these computing devices, when a cache block with modified data is to be used somewhere else in the computing device, the cache block is copied from the cache to the location where the cache block is to be used. By writing modified cache blocks in this way in the write-back mode, entities associated with the cache (e.g., processing subsystems, etc.) can make multiple writes/modifications to cache blocks without requiring that the cache blocks be immediately forwarded to the next lower level in the memory hierarchy each time a modification is made to the cache blocks. This can conserve bandwidth, processing time, etc. in the computing device. However, storing modified cache blocks in caches in this way introduces delay when the cache block is to be used somewhere else in the computing device and complicates operations that rely on the caches in the memory hierarchy holding consistent data.
As described above, straightforward implementations of the write-through mode and the write-back mode, while having some benefits, are also associated with significant detriments. To avoid some of the detriments associated with operating a cache in one mode or the other, designers have proposed determining whether to operate an entire cache in the write-through mode or the write-back mode based on a number of cache blocks with modified data in the cache. In this system, if the number of cache blocks with modified data in the cache is greater than a threshold number, the entire cache is switched to operating in the write-through mode. Otherwise, the entire cache is operated in a write-back mode. Despite providing some improvement over the straightforward implementation of write-back mode or write-through mode, this technique still incurs costs in terms of delay, bandwidth consumption, processing time, etc.
Designers have also proposed dividing a main memory in a device into a set of regions and statically configuring the regions in the main memory to operate either in the write-back mode or write-through mode (i.e., statically configuring caches in the device to handle writes of cache lines from the regions as either write-back or write-through). Despite providing some improvement over the straightforward implementation of write-back mode or write-through mode for the entire cache, this technique does not provide optimal performance as access patterns in the main memory vary at runtime.